
module wr_gen(
				  input         clk100k,
              input         rst_n,
				  output [23:0] odata,
				  output        wr,
				  input         wr_done
				  );
parameter REG_NUM = 84;//需要配置的寄存器数目
reg [2:0]  wr_s;
reg        wr_r;
reg [23:0] odata_r;
reg [9:0]  reg_cnt;
reg [31:0] dly_cnt; 
assign odata = odata_r;
assign wr    = wr_r;
always@(posedge clk100k or negedge rst_n)
begin
if(!rst_n)
    begin
	 wr_s <= 3'd0;
	 wr_r <= 1'b0;
	 reg_cnt <= 10'd0;
	 dly_cnt <= 0;
	 end
else
    begin
	 case(wr_s)
	 3'd0:begin
	     wr_r <= 1'b1;
		  wr_s <= 3'd1;
		  dly_cnt <= 0;
	 end
	 3'd1:begin
	     wr_r <= 1'b0;
		  wr_s <= 3'd2;
	 end
	 3'd2:begin
	     if(wr_done)
		      begin
				reg_cnt <= (reg_cnt < REG_NUM-1)?reg_cnt+10'd1:REG_NUM-1;
				wr_s    <= (reg_cnt < REG_NUM-1)?3'd3:3'd2;
				end
		  else
		      begin
				reg_cnt <= reg_cnt;
				wr_s    <= wr_s;
				end
	 end
	 3'd3:begin
	     if(reg_cnt == 10'd26)
		     wr_s <= 3'd4;
	     if(reg_cnt == 10'd27)
		     wr_s <= 3'd4;
		 if(reg_cnt == 10'd33)
		     wr_s <= 3'd4;
		 else
	         wr_s <= 3'd0;
	 end
	 3'd4:begin
	     if(dly_cnt < 150_000)
		     begin
		     dly_cnt <= dly_cnt+1;
			 wr_s <= 3'd4;
			 end
		 else
		     begin
		     dly_cnt <= 0   ;
			 wr_s    <= 3'd0;
			 end
	     
	 end
	 endcase
	 end
end
always@(*)
begin
case(reg_cnt)
10'd0:odata_r = 24'h8A7CA9;//进入第1页寄存器地址
10'd1:odata_r = 24'h8A1C04;//
10'd2:odata_r = 24'h8A0BE0;
10'd3:odata_r = 24'h8A0C2E;

10'd4:odata_r = 24'h8A7CA8;//回到第0页寄存器地址
10'd5:odata_r  = 24'h8A0200;
10'd6:odata_r  = 24'h8A0301;
10'd7:odata_r  = 24'h8A04C8;
10'd8:odata_r  = 24'h8A0500;
10'd9:odata_r  = 24'h8A0680;
10'd10:odata_r = 24'h8A0700;
10'd11:odata_r = 24'h8A08A9;
10'd12:odata_r = 24'h8A0901;
10'd13:odata_r = 24'h8A0A00;
10'd14:odata_r = 24'h8A0B00;
10'd15:odata_r = 24'h8A0C90;
10'd16:odata_r = 24'h8A0D01;
10'd17:odata_r = 24'h8A0E03;
10'd18:odata_r = 24'h8A1001;
10'd19:odata_r = 24'h8A1600;
10'd20:odata_r = 24'h8A200E;
10'd21:odata_r = 24'h8A2F00;
10'd22:odata_r = 24'h8A3024;
10'd23:odata_r = 24'h8A3102;
10'd24:odata_r = 24'h8A3300;
10'd25:odata_r = 24'h8A0101;


10'd26:odata_r = 24'h8A0180;
10'd27:odata_r = 24'h8A7CA8;//page0
10'd28:odata_r = 24'h8A1F00;
10'd29:odata_r = 24'h8A3515;
10'd30:odata_r = 24'h8A7CAB;//page3
10'd31:odata_r = 24'h8A20A5;
10'd32:odata_r = 24'h8A7CA8;//page0
10'd33:odata_r = 24'h8A7CAB;//page3
10'd34:odata_r = 24'h8A0B88;
10'd35:odata_r = 24'h8A1061;
10'd36:odata_r = 24'h8A1548;
10'd37:odata_r = 24'h8A1D05;
//10'd38:odata_r = 24'h8A0CA9;
10'd39:odata_r = 24'h8A7CA8;//page0

10'd40:odata_r = 24'h8A7CAB;//page3
10'd41:odata_r = 24'h8A0E3E;
10'd42:odata_r = 24'h8A10E1;
10'd43:odata_r = 24'h8A7CA8;//page0
10'd44:odata_r = 24'h8A2C05;
10'd45:odata_r = 24'h8A2420;
10'd46:odata_r = 24'h8A2520;

10'd47:odata_r = 24'h8A7CAB;//page3
10'd48:odata_r = 24'h8A1F60;
10'd49:odata_r = 24'h8A1707;
10'd50:odata_r = 24'h8A18FF;
10'd51:odata_r = 24'h8A19FF;
10'd52:odata_r = 24'h8A1AFF;
10'd53:odata_r = 24'h8A1BFF;
10'd54:odata_r = 24'h8A12F0;
10'd55:odata_r = 24'h8A1C02;
10'd56:odata_r = 24'h8A0C88;
10'd57:odata_r = 24'h8A1480;
10'd58:odata_r = 24'h8A0FDA;
10'd59:odata_r = 24'h8A0A88;
10'd60:odata_r = 24'h8A0720;
10'd61:odata_r = 24'h8A1300;
10'd62:odata_r = 24'h8A7CA9;//page1
10'd63:odata_r = 24'h8A3E80;
10'd64:odata_r = 24'h8A3F80;
10'd65:odata_r = 24'h8A4074;
10'd66:odata_r = 24'h8A7CA8;//page0
10'd67:odata_r = 24'h8A7CA9;//page1
10'd68:odata_r = 24'h8A575A;
10'd69:odata_r = 24'h8A7CA8;//page0

10'd70:odata_r = 24'h8A3E00;
10'd71:odata_r = 24'h8A416F;
10'd72:odata_r = 24'h8A4225;
10'd73:odata_r = 24'h8A430F;
10'd74:odata_r = 24'h8A441C;
10'd75:odata_r = 24'h8A45B3;
10'd76:odata_r = 24'h8A4622;
10'd77:odata_r = 24'h8A47CB;
10'd78:odata_r = 24'h8A481E;
10'd79:odata_r = 24'h8A4941;
10'd80:odata_r = 24'h8A2D30;//行周期101us,积分时间50us
10'd81:odata_r = 24'h8A2E00;//行周期101us,积分时间50us
10'd82:odata_r = 24'h8A4924;//设置全局NUC值
10'd83:odata_r = 24'h8A4010;//写入设置的全局NUC值到NUC SRAM
//10'd80:odata_r = 24'h8A3E80;
/*
10'd0:odata_r = 24'h8A7CA9;//进入第1页寄存器地址
10'd1:odata_r = 24'h8A1C04;//
10'd2:odata_r = 24'h8A0B40;
10'd3:odata_r = 24'h8A0C1F;
10'd4:odata_r = 24'h8A7CA8;//回到第0页寄存器地址
10'd5:odata_r = 24'h8A2DCC;//行周期101us,积分时间50us//
10'd6:odata_r = 24'h8A2E00;//行周期101us,积分时间50us
10'd7:odata_r = 24'h8A2803;
10'd8:odata_r = 24'h8A7CAB;//进入第3页寄存器地址
10'd9:odata_r = 24'h8A0F41;//高5bit为GSK，低3bit建议配置成“001”
10'd10:odata_r = 24'h8A12D0;//低5bit为HSSD，高3bit配置成“110”
10'd11:odata_r = 24'h8A1300;
10'd12:odata_r = 24'h8A170F;
10'd13:odata_r = 24'h8A18FF;
10'd14:odata_r = 24'h8A19FF;
10'd15:odata_r = 24'h8A1AFF;
10'd16:odata_r = 24'h8A1BFF;
10'd17:odata_r = 24'h8A7CA8;//回到第0页寄存器地址
10'd18:odata_r = 24'h8A0004;//时序冻结
10'd18:odata_r = 24'h8A0000;//结束时序冻结
10'd20:odata_r = 24'h8A0101;//“reg_initial_start”寄存器置‘1’
*/
default:odata_r = 24'h8A7CA8;
endcase
end
endmodule 